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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP40N10E/D Advance Data Sheet TMOS E-FET.TM Power Field Effect Transistor N-Channel Enhancement-Mode Silicon Gate This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature MTP40N10E TMOS POWER FET 40 AMPERES 100 VOLTS RDS(on) = 0.04 OHM (R) N-Channel D G S CASE 221A-06, Style 5 TO-220AB MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage -- Continuous Gate-to-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 40 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RJC RJA TL Value 100 100 20 40 40 29 140 169 1.35 - 55 to 150 800 0.74 62.5 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ C/W C This document contains information on a new product. Specifications and information herein are subject to change without notice. E-FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. REV 1 (c) Motorola TMOS Motorola, Inc. 1997 Power MOSFET Transistor Device Data 1 MTP40N10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ =125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 20 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 40 Adc) (VGS = 10 Vdc, ID = 20 Adc, TJ = 125C) Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) ( (VDS = 80 Vd , ID = 40 Adc, Vdc, Ad , VGS = 10 Vdc) Vdc, (VDD = 50 Vd ID = 40 Adc, Ad VGS = 10 Vdc Vdc, RG = 9.1 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 40 Adc, VGS = 0 Vdc) (IS = 40 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (See Figure 14) ( (IS = 40 Adc, VGS = 0 Vdc, Ad , Vd , dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. Max limit - Typ (3) Reflects typical values. Cpk 3 sigma LD -- -- LS -- 7.5 -- 3.5 4.5 -- -- nH trr ta tb QRR VSD -- -- -- -- -- -- 0.96 0.88 152 117 35 1.0 1.0 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 19 165 75 97 80 15 40 29 40 330 150 190 110 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc f = 1.0 MHz) Ciss Coss Crss -- -- -- 2305 620 205 3230 1240 290 pF (Cpk 2.0) (3) VGS(th) 2.0 -- (Cpk 2.0) (3) RDS(on) -- VDS(on) -- -- gFS 17 -- -- 21 1.9 1.7 -- mhos 0.033 0.04 Vdc 2.9 6.7 4.0 -- Vdc mV/C Ohms V(BR)DSS (Cpk 2.0) (3) IDSS -- -- IGSS -- -- -- -- 10 100 100 nAdc 100 -- -- 112 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit + 2 Motorola TMOS Power MOSFET Transistor Device Data MTP40N10E TYPICAL ELECTRICAL CHARACTERISTICS 80 70 I D , DRAIN CURRENT (AMPS) 60 50 40 6V 30 20 10 0 0 1 3 4 5 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 9 10 5V 7V I D , DRAIN CURRENT (AMPS) 9V VGS = 10 V 8V TJ = 25C 80 70 60 50 40 30 20 10 0 2 3 4 5 6 7 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 TJ = -55C VDS 10 V 100C 25C Figure 1. On-Region Characteristics R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.07 VGS = 10 V 0.06 TJ = 100C 0.05 0.04 0.03 0.02 0.01 0 0 10 20 30 40 50 60 70 80 ID, DRAIN CURRENT (AMPS) -55C 25C 0.050 0.045 0.040 0.035 0.030 15 V 0.025 0.020 0.015 0.010 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) 70 80 VGS = 10 V TJ = 25C Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 VGS = 10 V ID = 20 A I DSS , LEAKAGE (nA) 1000 VGS = 0 V TJ = 125C 100 100C 10 1.0 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 0 10 50 20 30 40 60 70 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 90 100 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3 MTP40N10E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8000 VDS = 0 V 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 -10 Crss -5 VGS 0 VDS 5 10 15 20 25 Coss Ciss Ciss Crss VGS = 0 V TJ = 25C The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data MTP40N10E VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 10 Q3 20 30 40 VDS 50 60 70 80 ID = 40 A TJ = 25C Q1 Q2 VGS QT 80 72 64 56 48 40 32 24 16 8 0 10,000 VDD = 50 V ID = 40 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) 1000 100 tr tf td(off) td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100 10 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 40 35 I S , SOURCE CURRENT (AMPS) 30 25 20 15 10 5 0 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) VGS = 0 V TJ = 25C Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. Motorola TMOS Power MOSFET Transistor Device Data 5 MTP40N10E SAFE OPERATING AREA 1000 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 100 100 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 ms 800 700 600 500 400 300 200 100 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) ID = 40 A 1.0 ms 10 10 ms dc 1.0 0.1 1.0 10 100 1000 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area 1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.0 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (seconds) P(pk) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTP40N10E PACKAGE DIMENSIONS -T- B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04 Q 123 A U K STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN H Z L V G D N R J CASE 221A-06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7 MTP40N10E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 - http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 8 Motorola TMOS Power MOSFET Transistor MTP40N10E/D Device Data |
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